Divs, Divq (Divide Primitive) - Analog Devices ADSP-BF53x Blackfin Reference

DIVS, DIVQ (Divide Primitive)

General Form
DIVS ( dividend_register, divisor_register )
DIVQ ( dividend_register, divisor_register )
Syntax
DIVS ( Dreg, Dreg ) ;
based on the signs of the 32-bit dividend and the 16-bit divisor.
Left shift the dividend one bit. Copy AQ into the dividend LSB.
(a) */
DIVQ ( Dreg, Dreg ) ;
tract the divisor from the dividend. Then set the AQ flag based
on the MSBs of the 32-bit dividend and the 16-bit divisor. Left
shift the dividend one bit. Copy the logical inverse of AQ into
the dividend LSB. (a) */
Syntax Terminology
:
Dreg R7–0
Instruction Length
In the syntax, comment (a) identifies 16-bit instruction length.
Functional Description
The Divide Primitive instruction versions are the foundation elements of a
nonrestoring conditional add-subtract division algorithm. See
on page 15-24
The dividend (numerator) is a 32-bit value. The divisor (denominator) is
a 16-bit value in the lower half of
half-word of
divisor_register
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
/* Initialize for DIVQ. Set the AQ flag
/* Based on AQ flag, either add or sub-
for such a routine.
is ignored entirely.
Arithmetic Operations
divisor_register
"Example"
. The high-order
15-19