Data Register File - Analog Devices ADSP-BF53x Blackfin Reference

Data Address Registers
Figure 2-3. Register Files

Data Register File

The Data Register File consists of eight registers, each 32 bits wide. Each
register may be viewed as a pair of independent 16-bit registers. Each is
denoted as the low half or high half. Thus the 32-bit register
regarded as two independent register halves,
For example, these instructions represent a 32-bit and a 16-bit operation:
R2 = R1 + R2;
R2.L = R1.H * R0.L;
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Address Arithmetic Unit Registers
I0 L0 B0
I1 L1 B1
I2 L2 B2
I3 L3 B3
Supervisor only register. Attempted read or
write in User mode causes an exception error.
/* 32-bit addition */
/* 16-bit multiplication */
Computational Units
Pointer
Registers
M0 P0
M1 P1
M2
P2
M3
P3
P4
P5
User SP
Supervisor SP
FP
and
R0.L
may be
R0
.
R0.H
2-7