Table 11-8 Dwt Current Pc Sampler Cycle Count Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

Bits Field Function
[31:0] CYCCNT Current PC Sampler Cycle Counter count value. When enabled, this counter counts the number of
core cycles, except when the core is halted.
CYCCNT is a free running counter, counting upwards. It wraps around to 0 on overflow.
The debugger must initialize this to 0 when first enabling.
ARM DDI 0337G
Unrestricted Access
Note
The TRCENA bit of the Debug Exception and Monitor Control Register must be set
before you can use the DWT. See Debug Exception and Monitor Control Register on
page 10-8.
Note
The DWT is enabled independently from the ITM. If you enable the DWT to emit
events, you must also enable the ITM.
DWT Current PC Sampler Cycle Count Register
Use the DWT Current PC Sampler Cycle Count Register to count the number of core
cycles. This count can measure elapsed execution time.
The register address, access type, and Reset state are:
Address
0xE0001004
Access Read/write
Reset state 0x00000000
Table 11-8 describes the bit assignments of the DWT Current PC Sampler Cycle Count
Register.

Table 11-8 DWT Current PC Sampler Cycle Count Register bit assignments

This is a free-running counter. The counter has three functions:
• When PCSAMPLENA is set, the PC is sampled and emitted when the selected
tapped bit changes value (0 to 1 or 1 to 0) and any post-scalar value counts to 0.
• When CYCEVTENA is set (and PCSAMPLENA is clear), an event is emitted
when the selected tapped bit changes value (0 to 1 or 1 to 0) and any post-scalar
value counts to 0.
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