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System Debug
Field
Name
[31:0]
CYCCNT
11-18
Table 11-8 describes the fields of the DWT Current PC Sampler Cycle Count Register.
Table 11-8 DWT Current PC Sampler Cycle Count Register bit assignments
Definition
Current PC Sampler Cycle Counter count value. When enabled, this counter counts the number of
core cycles, except when the core is halted.
DWT_CYCCNT is a free running counter, counting upwards. It wraps around to 0 on overflow.
The debugger should initialize this to 0 when first enabling.
This is a free-running counter. The counter has three functions:
•
When PCSAMPLENA is set, the PC is sampled and emitted when the selected
tapped bit changes value (0 to 1 or 1 to 0) and any post-scalar value counts to 0.
•
When CYCEVTENA is set (and PCSAMPLENA is clear), an event is emitted
when the selected tapped bit changes value (0 to 1 or 1 to 0) and any post-scalar
value counts to 0.
•
Can be used by applications and debuggers to measure elapsed execution time. By
subtracting a start and an end time, an application can measure time between
in-core clocks (other than when Halted in debug). This is valid to 2
cycles (for example, almost 82 seconds at 50MHz).
DWT CPI Count Register
Use the DWT CPI Count Register to count the total number of instruction cycles beyond
the first cycle.
The register address, access type, and Reset state are:
Address
0xE0001008
Access
Read-write
Reset state
-
Figure 11-6 shows the fields of the DWT CPI Count Register.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
Figure 11-6 DWT CPI Count Register bit assignments
32
core clock
ARM DDI 0337B
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