Table 17-10 Integration Test Register-Itatbctr2 Bit Assignments; Figure 17-8 Integration Test Register-Itatbctr2 Bit Assignments - ARM Cortex-M3 Technical Reference Manual

31
Bits Field
[31:1] -
[0] ATREADY1, ATREADY2
ARM DDI 0337G
Integration Test Registers
Use the Integration Test Registers to perform topology detection of the TPIU with other
devices in a Cortex-M3 system. These registers enable direct control of outputs and the
ability to read the value of inputs. The processor provides two Integration Test
Registers:
• Integration Test Register - ITATBCTR2
• Integration Test Register - ITATBCTR0.
Integration Test Register-ITATBCTR2
The register address, access type, and Reset state are:
Address 0xE0040EF0
Access Read only
Reset state
0x0
Figure 17-8 shows the bit assignments of the Integration Test Register bit assignments.

Figure 17-8 Integration Test Register-ITATBCTR2 bit assignments

Table 17-10 describes the bit assignments of the Integration Test Register bit
assignments.

Table 17-10 Integration Test Register-ITATBCTR2 bit assignments

Integration Test Register-ITATBCTR0
The register address, access type, and Reset state are:
Address
0xE0040EF8
Access Read only
Reset state 0x0
Copyright © 2005-2008 ARM Limited. All rights reserved.
Reserved
Function
Reserved.
This bit reads or sets the value of ATREADYS1 and ATREADYS2.
Trace Port Interface Unit
1 0
ATREADY1
ATREADY2
17-15