About The Programmer's Model - ARM PrimeCelL PL320 Technical Reference Manual

Programmer's Model
3.1

About the programmer's model

3-2
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The following applies to the IPCM registers:
• The base address of the IPCM is not fixed and can be different for any particular
system implementation. However, the offset of any particular register from the
base address is fixed.
• Reserved or unused address locations must not be accessed because this can result
in unpredictable behavior of the device.
• Reserved or unused bits of registers must be written as zero, and ignored on read
unless otherwise stated in the relevant text.
• All register bits are reset to a 0 by a system or power-on reset unless otherwise
stated in the relevant text.
• All registers support read and write accesses unless otherwise stated in the
relevant text. A write updates the contents of a register and a read returns the
contents of the register.
Note
Only Mailbox0 and the Interrupt Status registers for Interrupt0 are fully expanded for
clarity. However, Mailboxes 1-31 at offsets
also exist, depending on your configuration.
0x808-0x8FC
Because of the highly configurable nature of the IPCM, all the registers shown here
might not be available in every configuration of the IPCM. Any writes to unavailable
registers are ignored and any reads of unavailable registers return
MBOXNUM defines which Mailbox Registers are available. For example, when
MBOXNUM is set to 1, only Mailbox0 Registers is available. When MBOXNUM is
set to 32, all Mailbox Registers are available.
INTNUM defines the bit width of the IPCMxSOURCE, IPCMxDCLEAR,
IPCMxDSET, IPCMxDSTATUS, IPCMxMCLEAR, IPCMxMSET, and
IPCMxMSTATUS Registers. For example, when INTNUM is set to 1, the registers
listed above are all only a single bit wide (bit0). Setting INTNUM to 32 sets the
registers to 32 bits wide.
Secondly, INTNUM defines which IPCMRISx and IPCMMISx registers are available.
For example, when INTNUM is set to 1, only the IPCMRIS0 and IPCMMIS0 Registers
are available. When INTNUM is set to 32, all IPCMRIS0 to IPCMRIS31 Registers and
IPCMMIS0 to IPCMMIS31 registers are available.
Copyright © 2003, 2004. ARM Limited. All rights reserved.
, and Interrupt 1-31 at offsets
0x040-0x7FC
0x00000000
.
ARM DDI 0306B