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Programmer's Model
2.1
About the programmer's model
2.1.1
Operating modes
2.1.2
Operating states
2-2
The processor implements the ARM v7-M Architecture. This includes the entire 16-bit
Thumb instruction set and the base Thumb-2 32-bit instruction set architecture. The
processor cannot execute ARM instructions.
The Thumb instruction set is a subset of the ARM instruction set, re-encoded to 16 bits.
It supports higher code density and systems with memory data buses that are 16 bits
wide or narrower.
Thumb-2 is a major enhancement to the Thumb Instruction Set Architecture (ISA).
Thumb-2 enables higher code density than Thumb and offers higher performance with
16/32-bit instructions.
The processor supports two modes of operation, Thread mode and Handler mode:
•
Thread mode is entered on Reset, and can be entered as a result of an exception
return. Privileged and User (Unprivileged) code can run in Thread mode.
•
Handler mode is entered as a result of an exception. All code is privileged in
Handler mode.
The Cortex-M3 processor can operate in one of two operating states:
•
Thumb state. This is normal execution running 16-bit and 32-bit halfword aligned
Thumb and Thumb-2 instructions.
•
Debug State. When in halting debug.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
ARM DDI 0337B
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