Table 10-2 Debug Halting Control And Status Register; Figure 10-1 Debug Halting Control And Status Register Format - ARM Cortex-M3 Technical Reference Manual

Core Debug
Bit
R/W Field name
range
[31:16] W DBGKEY
[31:26] - -
[25] R S_RESET_ST
[24] R S_RETIRE_ST
[23:20] - -
[19] R S_LOCKUP
10-4

Figure 10-1 Debug Halting Control and Status Register format

Table 10-2 shows the bit functions of the Debug ID Register.
Function
Debug Key.
status bits [25:16]. If not written as Key, the write operation is ignored and no bits
are written into the register.
Reserved, RAZ.
Indicates that the core has been reset, or is now being reset, since the last time this
bit was read. This a sticky bit that clears on read. So, reading twice and getting 1
then 0 means it was reset in the past. Reading twice and getting 1 both times means
that it is being reset now (held in reset still).
Indicates that an instruction has completed since last read. This is a sticky bit that
clears on read. This is used to determine if the core is stalled on a load/store or
fetch.
Reserved, RAZ.
Reads as one if the core is running (not halted) and a lockup condition is present.
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Table 10-2 Debug Halting Control and Status Register

must be written anytime this register is written. Reads back as
0xA05F
ARM DDI 0337B