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Bits
Field
[9:8]
TSPrescale
[7:5]
-
[4]
SWOENA
[3]
DWTENA
[2]
SYNCENA
[1]
TSENA
[0]
ITMENA
31
ARM DDI 0337G
Unrestricted Access
Table 11-22 ITM Trace Control Register bit assignments (continued)
Function
Timestamp prescaler:
0b00 = no prescaling
0b01 = divide by 4
0b10 = divide by 16
0b11 = divide by 64.
Reserved.
Enable SWV behavior – count on TPIUACTV and TPIUBAUD.
Enables the DWT stimulus.
Enables sync packets for TPIU.
Enables differential timestamps. Differential timestamps are emitted when a packet is written
to the FIFO with a non-zero timestamp counter, and when the timestamp counter overflows.
Timestamps are emitted during idle times after a fixed number of two million cycles. This
provides a time reference for packets and inter-packet gaps.
If SWOENA (bit [4]) is set, timestamps are triggered by activity on the internal trace bus only.
In this case there is no regular timestamp output when the ITM is idle.
Enable ITM. This is the master enable, and must be set before ITM Stimulus and Trace Enable
registers can be written.
Note
DWT is not enabled in the ITM block. However, DWT stimulus entry into the FIFO is
controlled by DWTENA. If DWT requires timestamping, the TSSEN bit must be set.
ITM Integration Write Register
Use this register to determine the behavior of the ATVALIDM bit.
Figure 11-15 shows the ITM Integration Write Register bit assignments.
Figure 11-15 ITM Integration Write Register bit assignments
Copyright © 2005-2008 ARM Limited. All rights reserved.
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System Debug
1
0
ATVALIDM
11-35
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