Figure 3-15 Data Write Bus Cycle; Figure 3-16 Data Bus Control Circuit - ARM ARM7TDMI Technical Reference Manual

Memory Interface
3-20
A[31:0]
nENOUT
D[31:0]
ARM7TDMI
Data direction
control from core
Write data
from core
Read data
Copyright © 2001, 2004 ARM Limited. All rights reserved.
MCLK
nRW
to core

Figure 3-16 Data bus control circuit

memory cycle

Figure 3-15 Data write bus cycle

Scan
cell
Scan
cell
Scan
cell
ARM DDI 0210C
DBE
nENOUT
nENIN
TBE
D[31:0]