B2.69 Id_Isar4_El1, Aarch32 Instruction Set Attribute Register 4, El1 - ARM Cortex-A76 Core Technical Reference Manual

B2.69 ID_ISAR4_EL1, AArch32 Instruction Set Attribute Register 4, EL1
The ID_ISAR4_EL1 provides information about the instruction sets implemented by the core in
AArch32.
Bit field descriptions
ID_ISAR4_EL1 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
SWP_frac, [31:28]
PSR_M, [27:24]
SynchPrim_frac, [23:20]
Barrier, [19:16]
SMC, [15:12]
WriteBack, [11:8]
WithShifts, [7:4]
100798_0300_00_en
31 28 27 24 23
SWP_frac PSR_M
SynchPrim_frac
Indicates support for the memory system locking the bus for
and instructions not implemented.
0x0 SWP SWPB
Indicates the implemented M profile instructions to modify the PSRs:
None implemented.
0x0
This field is used with the ID_ISAR3.SynchPrim field to indicate the implemented
Synchronization Primitive instructions:
• The and
0x0 LDREX
• The ,
CLREX LDREXB
• The and
LDREXD
Indicates the supported Barrier instructions in the A32 and T32 instruction sets:
The , , and
0x1 DMB DSB
Indicates the implemented
None implemented.
0x0
Indicates the support for Write-Back addressing modes:
Core supports all the Write-Back addressing modes as defined in Armv8-A.
0x1
Indicates the support for instructions with shifts.
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B2.69 ID_ISAR4_EL1, AArch32 Instruction Set Attribute Register 4, EL1

20 19 16 15
Barrier SMC
Figure B2-53 ID_ISAR4_EL1 bit assignments
instructions.
STREX
, , , and
LDREXH STREXB
instructions.
STREXD
barrier instructions.
ISB
instructions:
SMC
reserved.
Non-Confidential
B2 AArch64 system registers
12 11 8 7 4 3
WriteBack WithShifts
or instructions:
SWP SWPB
instructions.
STREXH
0
Unpriv
B2-241