Figure 2-7 Configuration, Back-To-Back Messaging From Core0 To Core1 - ARM PrimeCelL PL320 Technical Reference Manual

Inter-processor communications module

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Functional Overview

2.3.2

Back-to-back messaging from Core0 to Core1

2-20

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12.

Core0 clears bit 1 in the Mailbox Send Register to clear its interrupt.

13.

Core0 releases ownership of the mailbox by clearing the IPCM0SOURCE

IPCM0DR0 Registers.

Note

Core0 can hold on to the mailbox to send another data message by not clearing the

IPCM0SOURCE Register at step 13.

In this example system, there are two cores and four mailboxes. Core0 is the source core

and Core1 is the destination core. Core0 uses Channel ID1 and Core1 uses Channel ID2,

as in Back-to-back messaging from Core0 to Core1. Core0 sends a message to Core1,

obtains an acknowledge, and sends another message to Core1, which is also

acknowledged. This example assumes that the IPCM is not in integration test mode.

Mailboxes 1-3 are inactive and Auto Acknowledge and Auto Link are disabled.

Figure 2-7 shows the configuration.

A HB bus

Figure 2-7 Configuration, back-to-back messaging from Core0 to Core1

Figure 2-8 on page 2-21 shows the messaging sequence.

IPCM INT[0]

IPCM INT[1]

Interrupt

controller0

controller1

Core0

Core1

IPCM

Minimum

conf iguration:

MBOXNUM=4

INTNUM=2

DA TA NUM=1

ARM DDI 0306B

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