Chapter A6; Level 1 Memory System - ARM Cortex-A76 Core Technical Reference Manual

Table of Contents

Advertisement

Chapter A6

Level 1 memory system

This chapter describes the L1 instruction cache and data cache that make up the L1 memory system.
It contains the following sections:
A6.1 About the L1 memory system on page
A6.2 Cache behavior on page
A6.3 L1 instruction memory system on page
A6.4 L1 data memory system on page
A6.5 Data prefetching on page
A6.6 Direct access to internal memory on page
100798_0300_00_en
A6-73.
A6-77.
A6-79.
Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
Non-Confidential
A6-72.
A6-75.
A6-80.
A6-71

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the Cortex-A76 Core and is the answer not in the manual?

Subscribe to Our Youtube Channel

Table of Contents

Save PDF