D9.8 Trccidcctlr0, Context Id Comparator Control Register 0 - ARM Cortex-A76 Core Technical Reference Manual

D9.8 TRCCIDCCTLR0, Context ID Comparator Control Register 0
The TRCCIDCCTLR0 controls the mask value for the context ID comparators.
Bit field descriptions
The TRCCIDCCTLR0 is a 32-bit register.
RES0, [31:4]
COMP0, [3:0]
Bit fields and details not provided in this description are architecturally defined. See the Arm
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCCIDCCTLR0 can be accessed through the external debug interface, offset
100798_0300_00_en
31
0
RES
Reserved.
RES0
Controls the mask value that the trace unit applies to TRCCIDCVR0. Each bit in this field
corresponds to a byte in TRCCIDCVR0. When a bit is:
The trace unit includes the relevant byte in TRCCIDCVR0 when it performs the
0
Context ID comparison.
The trace unit ignores the relevant byte in TRCCIDCVR0 when it performs the
1
Context ID comparison.
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D9.8 TRCCIDCCTLR0, Context ID Comparator Control Register 0

Figure D9-7 TRCCIDCCTLR0 bit assignments
reserved.
Non-Confidential
D9 ETM registers
4 3 0
COMP0
®
.
0x680
D9-507