Figure 5-17 Cycle Timing Of Circuit That Uses Wait States For Non Sequential Accesses - ARM ARM926EJ-S Technical Reference Manual

Tightly-Coupled Memory Interface
CLK
IRCS
IRSEQ
IRWAIT
IRADDR
IRRD

Figure 5-17 Cycle timing of circuit that uses wait states for non sequential accesses

5.5.5 DMA interface example
5-26
T1 T2
A
CS
A
RD
Figure 5-18 on page 5-27 shows an example TCM subsystem using the DMA interface.
The signal driving DRDMAEN is connected to both the DRDMAEN and DRDMACS
inputs. It is also used to control the multiplexing of the non timing critical signals
(WBL, nRW, and WD), although this is not shown for clarity.
Copyright © 2001-2003 ARM Limited. All rights reserved.
T3 T4
A+1
A A+1 A+2
I(A) I(A+1)
I(A) I(A+1)
T5 T6 T7
A+2 A+3
A+3
I(A+2)
I(A+2)
ARM DDI0198D
A+4
A+4
I(A+3)
I(A+3)