Etm Interface Signals; Table A-6 Etm Interface Signals - ARM ARM926EJ-S Technical Reference Manual

Signal Descriptions
A.7

ETM interface signals

A-12
Table A-6 describes the ARM926EJ-S processor ETM interface signals.
Name
ETMBIGEND
ETMCHSD[1:0]
ETMCHSE[1:0]
ETMDA[31:0]
ETMDABORT
ETMDBGACK
ETMDMAS[1:0]
ETMDMORE
ETMDnMREQ
ETMDnRW
ETMDSEQ
ETMEN
ETMHIVECS
ETMIA[31:0]
ETMIABORT
ETMID15TO11[15:11]
ETMID31TO25[31:25]
ETMIJBIT
ETMInMREQ
ETMINSTREXEC
ETMINSTRVALID
ETMISEQ
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Direction Description
Output ETM big-endian configuration indication.
Output ETM coprocessor handshake decode signals.
Output ETM coprocessor handshake execute signals.
Output ETM data address.
Output ETM data abort.
Output ETM debug mode indication.
Output ETM data size indication.
Output ETM more sequential data indication.
Output ETM data memory request.
Output ETM data not read/write.
Output ETM sequential data indication.
Input Synchronous ETM interface enable. This signal
must be tied LOW if an ETM is not used.
Output ETM exception vectors configuration.
Output ETM instruction address.
Output ETM instruction abort.
Output ETM instruction data field bits [15:11].
Output ETM instruction data field bits [31:25].
Output ETM Jazelle state indication.
Output ETM instruction memory request.
Output ETM instruction execute indication.
Output ETM instruction valid indication.
Output ETM sequential instruction access.

Table A-6 ETM interface signals

ARM DDI0198D