Table of Contents
Advertisement
1.2
Reset signals
There are two types of reset signals available on ARM devices. DSTREAM expects these signals to be
wired in a certain way.
This section contains the following subsections:
•
1.2.1 ARM reset signals on page
•
1.2.2 DSTREAM reset signals on page
•
1.2.3 Example reset circuits on page
1.2.1
ARM reset signals
All ARM processors have a main processor reset that might be called nRESET, BnRES, or HRESET.
This is asserted by one or more of these conditions:
•
Power on.
•
Manual push button.
•
Remote reset from the debugger (using DSTREAM).
•
Watchdog circuit (if appropriate to the application).
Any ARM processor including the JTAG interface has a second reset input called nTRST (TAP Reset).
This resets the EmbeddedICE logic, the Test Access Port (TAP) controller, and the boundary scan cells. It
is activated by remote JTAG reset (from DSTREAM).
ARM strongly recommends that both signals are separately available on the JTAG connector. If the
nRESET and nTRST signals are linked together, resetting the system also resets the TAP controller.
This means that:
•
It is not possible to debug a system from reset, because any breakpoints previously set are lost.
•
You might have to start the debug session from the beginning, because DSTREAM might not recover
when the TAP controller state is changed.
Related references
1.2.2 DSTREAM reset signals on page 1-16.
1.2.3 Example reset circuits on page 1-17.
1.2.2
DSTREAM reset signals
The DSTREAM unit has two reset signals connected to the debug target hardware, nTRST and nSRST.
What the signals do:
•
nTRST drives the JTAG nTRST signal on the ARM processor. It is an output that is activated
whenever the debug software has to re-initialize the debug interface in the target system.
•
nSRST is a bidirectional signal that both drives and senses the system reset signal on the target. By
default, this output is driven LOW by the debugger to re-initialize the target system.
The target hardware must pull the reset lines to their inactive state to assure normal operation when the
JTAG interface is disconnected. In the DSTREAM unit, the strong pull-up/pull-down resistance is
approximately 33Ω, and the weak pull-up/pull-down resistance is approximately 4.7kΩ. Because you can
select the drive strength for nTRST and nSRST, target assemblies with a variey of different reset
configurations can be supported.
Related references
1.2.1 ARM reset signals on page 1-16.
1.2.3 Example reset circuits on page 1-17.
Related information
Debug hardware Advanced configuration reset options.
ARM 100956_0527_00_en
1-16.
1-17.
Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved.
Non-Confidential
1 ARM DSTREAM System Design Guidelines
1-16.
1.2 Reset signals
1-16
Advertisement
Table of Contents
