ARM Cortex M23 Manuals

Manuals and User Guides for ARM Cortex M23. We have 1 ARM Cortex M23 manual available for free PDF download: Generic User Manual

ARM Cortex M23 Generic User Manual (162 pages)

Processor Device

Brand: ARM | Category: Computer Hardware | Size: 1 MB

Table of Contents
5
Introduction
11
Implementation Obligations
11
Product Revision Status
11
Intended Audience
11
Conventions
12
Useful Resources
14
Cortex-M23 Devices Generic User Guide Introduction
15
About the Cortex-M23 Processor and Core Peripherals
15
The Cortex-M23 Processor
20
Programmers Model
20
Processor Modes and Privilege Levels for Software Execution
20
Stacks
21
Core Registers
22
General-Purpose Registers
23
Stack Pointer
23
Link Register
23
Program Counter
24
Program Status Register
24
Application Program Status Register
25
Interrupt Program Status Register
25
Execution Program Status Register
26
Interruptible-Restartable Instructions
27
Exception Mask Register
27
Priority Mask Register
27
CONTROL Register
28
Exceptions and Interrupts
29
Data Types
29
The Cortex Microcontroller Software Interface Standard
30
Memory Model
31
Memory Regions, Types, and Attributes
32
Device Memory
32
Behavior of Memory Accesses
34
Additional Memory Access Constraints for Caches and Shared Memory
35
Software Ordering of Memory Accesses
36
Memory Endianness
37
Byte-Invariant Big-Endian Format
37
Little-Endian Format
37
Synchronization Primitives
37
Programming Hints for the Synchronization Primitives
40
Exception Model
40
Exception States
40
Exception Types
41
Exception Handlers
43
Vector Table
44
Exception Priorities
46
Exception Entry and Return
47
Exception Entry
47
Exception Return
50
Fault Handling
51
Lockup
53
Power Management
53
Entering Sleep Mode
53
Wait for Event
54
Sleep-On-Exit
54
Wakeup from Sleep Mode
55
Wakeup Interrupt Controller
55
External Event Input
56
Power Management Programming Hints
56
The Cortex-M23 Instruction Set
57
Instruction Set Summary
57
CMSIS Functions
60
Cmse
62
About the Instruction Descriptions
62
Operands
62
Restrictions When Using PC or SP
63
Shift Operations
63
Asr
63
Lsr
64
Lsl
65
Ror
65
Address Alignment
66
PC-Relative Expressions
66
Conditional Execution
66
The Condition Flags
67
Condition Code Suffixes
68
Memory Access Instructions
68
Adr
69
Clrex
70
LDR and STR, Immediate Offset
71
LDR and STR Operation
71
LDR and STR, Register Offset
72
LDR, PC-Relative
73
LDR, PC-Relative Operation
73
LDM and STM
74
LDM and STM Restrictions
74
LDM and STM Examples
75
LDREX and STREX
75
LDA and STL
77
LDAEX and STLEX
78
PUSH and POP
80
General Data Processing Instructions
81
ADC, ADD, RSB, SBC, and SUB
82
ADC, ADD, RSB, SBC, and SUB Restrictions
83
ADC, ADD, RSB, SBC, and SUB Examples
83
AND, ORR, EOR, and BIC
84
ASR, LSL, LSR, and ROR
85
CMP and CMN
86
MOV and MVN
87
Movt
89
Muls
89
REV, REV16, and REVSH
90
SDIV and UDIV
91
SXT and UXT
92
Tst
93
Branch and Control Instructions
94
B, BL, BX, and BLX
94
B, BL, BX, and BLX Operation
95
BXNS and BLXNS
96
CBZ and CBNZ
97
Miscellaneous Instructions
98
Bkpt
98
Cps
99
Dmb
100
Dsb
100
Isb
101
Mrs
101
Msr
102
Nop
103
Sev
103
Svc
105
TT, TTT, TTA, and TTAT
105
Wfe
107
Wfi
108
Cortex-M23 Peripherals
109
About the Cortex-M23 Peripherals
109
Nested Vectored Interrupt Controller
110
Accessing the Cortex-M23 NVIC Registers Using CMSIS
111
Interrupt Set-Enable Registers
112
Interrupt Clear-Enable Registers
113
Interrupt Set-Pending Registers
113
Interrupt Clear-Pending Registers
114
Interrupt Active Bit Registers
115
Interrupt Target Non-Secure Registers
116
Interrupt Priority Registers
116
Level-Sensitive and Pulse Interrupts
117
Hardware and Software Control of Interrupts
118
NVIC Usage Hints and Tips
119
NVIC Programming Hints
119
System Control Space
119
CPUID Register
120
Interrupt Control and State Register
121
Vector Table Offset Register
124
Application Interrupt and Reset Control Register
125
System Control Register
127
Configuration and Control Register
128
System Handler Priority Registers
129
System Handler Priority Register 2
130
System Handler Priority Register 3
130
System Handler Control and State Register
130
Auxiliary Control Register
132
SCS Usage Hints and Tips
133
System Timer, Systick
133
Systick Control and Status Register
134
Systick Reload Value Register
135
Calculating the RELOAD Value
135
Systick Current Value Register
135
Systick Calibration Value Register
136
Systick Usage Hints and Tips
137
Security Attribution and Memory Protection
137
Security Attribution Unit
137
Security Attribution Unit Control Register
138
Security Attribution Unit Type Register
139
Security Attribution Unit Region Number Register
140
Security Attribution Unit Region Base Address Register
140
Security Attribution Unit Region Limit Address Register
141
Memory Protection Unit
141
MPU Type Register
143
MPU Control Register
143
MPU Region Number Register
145
MPU Region Base Address Register
145
MPU Region Limit Address Register
146
MPU Memory Attribute Indirection Register 0 and MPU Memory Attribute Indirection Register
147
MPU Mismatch
150
Updating a Protected Memory Region
150
MPU Design Hints and Tips
151
MPU Configuration for a Microcontroller
151
I/O Port
152
Functional Safety Features
153
About Functional Safety Features
153
Configuration
153
Interface Protection
156
Flop Parity
157
STL Support Components
158
FUSAEN I/O for Debug and Trace Logic Protection
159
STL Registers
159
Appendix A Revisions
162

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