Table B-4 Encoding Of The Main Tlb Entry-Select Bit Fields; Figure B-2 Rd Format For Selecting Main Tlb Entry - ARM ARM926EJ-S Technical Reference Manual

CP15 Test and Debug Registers
Instruction
MRC p15, 4/5, <Rd>, c15, c4, 0
MCR p15, 4/5, <Rd>, c15, c5, 0
MCR p15, 4/5, <Rd>, c15, c7, 0
MRC P15, 4/5, <Rd>, c15, c2, 1
MCR P15, 4/5, <Rd>, c15, c3, 1
MRC P15, 4/5, <Rd>, c15, c4, 1
MCR P15, 4/5, <Rd>, c15, c5, 1
MCR P15, 4/5, <Rd>, c15, c7, 1
31
B-6
Inserting or reading entries in the main TLB
Use this procedure to access entries in the main TLB:
1. Use the following Debug and Test Address Register instruction to access a main
TLB entry:
MCR p15, 0, <Rd>, c15, c1, 0 ; select TLB entry
The Rd register selects the main TLB entry as Figure B-2 shows.
30
SBZ
Way
Table B-4 describes the Rd register entry-select bit fields.
Bit Name
[31] Way
Copyright © 2001-2003 ARM Limited. All rights reserved.
Table B-3 MMU test operation instructions (continued)
Operation
Read PA and access permission data in main TLB entry
Write PA and access permission data data in main TLB entry
Transfer main TLB entry into RAM
Read tag in lockdown TLB entry
Write tag in lockdown TLB entry
Read PA and access permission data in lockdown TLB entry
Write PA and access permission data in lockdown TLB entry
Transfer lockdown TLB entry into RAM
15 14
Indexed entry

Figure B-2 Rd format for selecting main TLB entry

Table B-4 Encoding of the main TLB entry-select bit fields

Definition
Way select:
1 = way 1
0 = way 0.
10 9
SBZ
ARM DDI0198D
0