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A.2
Data memory interface signals
Name
Direction
DA[31:0]
Output
DABE
Input
DABORT
Input
DD[31:0]
Output
DDBE
Input
DDEN
Output
DDIN[31:0]
Input
DLOCK
Output
DMAS[1:0]
Output
DMORE
Output
DnM[4:0]
Output
ARM DDI0145B
Description
Data Address Bus. This is the processor data address bus. It changes when GCLK is
HIGH.
Data Address Bus Enable. When LOW, this input puts the data address bus, DA[31:0],
drivers into a high impedance state. This signal has the same effect on DnTRANS,
DLOCK, DMAS[1:0], DnRW, and DnM[4:0]. If UNIEN is HIGH this signal is
ignored.
Data Abort. This input allows the memory system to tell the processor that the
requested data memory access is not allowed.
Data Output Bus. This output bus is used to transfer write data between the processor
and external memory. The output data will become valid during phase 1 and remain
valid through GCLK phase 2.
If UNIEN is LOW, this is a tristate output bus and is only driven during write cycles.
If UNIEN is HIGH, this bus is always driven.
Data Data Bus Enable. This is an input which, when LOW, puts the Data Data Bus
DD[31:0] into a high impedance state. If UNIEN is HIGH this signal is ignored.
Data Data Bus Output Enabled. This signal indicates when the processor is
performing a write transfer on the Data Data Bus, DD[31:0].
Data Input Bus. This input is used to transfer load data between external memory and
the processor. It should be driven with the requested data by the end of GCLK phase
2.
Data Lock. If HIGH at the end of GCLK phase 2, any data memory access in the
following cycle is locked, and the memory controller must wait until DLOCK goes
LOW before allowing another device to access memory.
Data Memory Access Size. These outputs encode the size of a data memory access in
the following cycle. A word access is encoded as 10 (binary), a halfword access as 01,
and a byte access as 00. The encoding 11 is reserved.
Data More. If HIGH at the end of GCLK phase 2, the data memory access in the
following cycle will be directly followed by a sequential data memory access.
Data Mode. The processor mode within which the data memory access should be
performed.
Note that the data memory access mode may differ from the current processor mode.
Copyright © 1998, 1999 ARM Limited. All rights reserved.
ARM9TDMI Signal Descriptions
Table A-2 Data memory interface signals
A-3
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