D2.2 Dbgbcrn_El1, Debug Breakpoint Control Registers, El1 - ARM Cortex-A76 Core Technical Reference Manual

Name
DBGBVR5_EL1
DBGBCR5_EL1
OSECCR_EL1
MDCCSR_EL0
DBGDTR_EL0
DBGDTRTX_EL0
DBGDTRRX_EL0
MDRAR_EL1
OSLAR_EL1
OSLSR_EL1
OSDLR_EL1
DBGPRCR_EL1
DBGCLAIMSET_EL1
DBGCLAIMCLR_EL1
DBGAUTHSTATUS_EL1 RO
100798_0300_00_en
Type Reset Width Description
RW - 64
RW UNK 32
0x00000000 32
RW
0x00000000 32
RO
0x00000000 64
RW
0x00000000 32
WO
0x00000000 32
RO
RO 64
-
WO - 32
0x0000000A 32
RO
0x00000000 32
RW
RW - 32
0x000000FF 32
RW
0x00000000 32
RW
0x000000AA 32
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Table D2-1 AArch64 debug register summary (continued)
Debug Breakpoint Value Register 5

D2.2 DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1

on page D2-408
Debug OS Lock Exception Catch Register
Monitor Debug Comms Channel Status Register
Debug Data Transfer Register, half-duplex
Debug Data Transfer Register, Transmit, Internal View
Debug Data Transfer Register, Receive, Internal View
Debug ROM Address Register. This register is reserved,
Debug OS Lock Access Register
Debug OS Lock Status Register
Debug OS Double Lock Register
Debug Power/Reset Control Register
D2.3 DBGCLAIMSET_EL1, Debug Claim Tag Set Register, EL1
on page D2-411
Debug Claim Tag Clear Register
Debug Authentication Status Register
reserved.
Non-Confidential
D2 AArch64 debug registers
D2.1 AArch64 debug register summary
RES0
D2-407