Figure 8-5 Watchpoint Entry With Data Processing Instruction - ARM ARM966E-S Technical Reference Manual

8.4.3 Watchpoints
F1
CLK
InMREQ
NSTR[31:0]
1
DA[31:0]
WDATA[31:0]
RDATA[31:0]
DBGDEWPT
DBGACK
ARM DDI 0186A
Entry into debug state following a watchpointed memory access is imprecise. This is
necessary because of the nature of the pipeline.
External logic, such as external watchpoint comparators, can be built to extend the
functionality of the EmbeddedICE-RT logic. Their output must be applied to the
DBGDEWPT input. This signal is simply ORed with the internally-generated
Watchpoint signal before being applied to the ARM9E-S core control logic. The timing
of the input makes it unlikely that data-dependent external watchpoints are possible.
After a watchpointed access, the next instruction in the processor pipeline is always
allowed to complete execution. Where this instruction is a single-cycle data-processing
instruction, entry into debug state is delayed for one cycle while the instruction
completes. The timing of debug entry following a watchpointed load in this case is
shown in Figure 8-5.
D1 E1 M1
F2 D2 E2
Fldr Dldr
FDp
2 LDR Dp

Figure 8-5 Watchpoint entry with data processing instruction

Note
Although instruction 5 enters the Execute stage, it is not executed, and there is no state
update as a result of this instruction. When the debugging session is complete, normal
continuation involves a return to instruction 5, the next instruction in the code sequence
to be executed.
Copyright © 2000 ARM Limited. All rights reserved.
W1
M2 W2
Eldr Mldr Wldr
DDp EDp MDp
F5 D5 E5
5 6 7
WDp
M5 W5
Ddebug Edebug1
8
Debug Support
Edebug2
8-11