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2.2
Clocks
The MPS2 and MPS2+ FPGA Prototyping Boards each provide three programmable on‑board clock
generators.
Overview of clocks
Three clock generators on the MPS2 and MPS2+ FPGA Prototyping Boards and other clock generators
inside the FPGA generate the clocks that the board uses. The MCC configures the programmable clock
generators during powerup sequencing using values that the configuration files define.
You configure the frequencies of the on‑board clock generators by editing the OSCLKS section of the
application note
You can bypass the on‑board clock generators and import external clocks to the MCC board using the
connection headers that the MPS2 and MPS2+ FPGA Prototyping Boards provide.
The following figure shows the clocks on the MPS2 and MPS2+ FPGA Prototyping Boards. The figure
shows two of the clock generators that connect to PLLs inside the FPGA with external loopback to logic
inside the FPGA. The third clock generator connects directly to logic inside the FPGA.
•
The slide switches and connection headers are for general‑purpose use. You can use them for any
purpose whatsoever according to the needs of the design which you implement in the FPGA.
•
The availability of clock generators and logic in the FPGA depend on the design which you
implement in the FPGA.
100112_0200_09_en
file in the microSD card.
.txt
Note
MPS2/MPS2+ FPGA Prototyping Board
Copyright © 2013–2016, 2018–2020 Arm Limited or its affiliates. All
rights reserved.
Non-Confidential
OSC0
Slide switch
J22
Connection
header
J18
V
SS
OSC1
Slide switch
J23
Connection
header
J19
V
SS
OSC2
2 Hardware Description
2.2 Clocks
PLL
Logic
PLL
Logic
Logic
FPGA
Figure 2-2 Board clocks
2-25
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