Dmaenable Setup And Hold Cycles; Table 5-2 Dmaenable Setup And Hold Cycles With Respect To Dmanreq - ARM ARM966E-S Technical Reference Manual

5.3

DMAENABLE setup and hold cycles

ARM DDI 0186A
Table 5-2 shows the minimum number of setup cycles and hold cycles for
DMAENABLE with respect to DMAnREQ for both single and dual-port RAMs.

Table 5-2 DMAENABLE setup and hold cycles with respect to DMAnREQ

Operation
Dual-port RAM DMA read
Dual-port RAM DMA write
Single-port RAM DMA read
Single-port RAM DMA write
To reduce power consumption, DMAENABLE must be taken LOW when DMA
accesses are not taking place or if DMA is not implemented.
Copyright © 2000 ARM Limited. All rights reserved.
Setup
1
1
1
1
Direct Memory Access (DMA)
Hold
1
0
1
0
5-11