Chapter 6 Clocking And Resets; Cortex-M3 Clocking; Table 6-1 Cortex-M3 Processor Clocks; Table 6-2 Cortex-M3 Macrocell Clocks - ARM Cortex-M3 Technical Reference Manual

Clocking and Resets
6.1

Cortex-M3 clocking

Clock Domain
FCLK Processor
HCLK Processor
DAPCLK Processor
6-2
The processor has three functional clock inputs. These are described in Table 6-1.
Description
Free running processor clock, used for sampling interrupts and clocking debug blocks. FCLK
ensures that interrupts can be sampled, and sleep events can be traced, while the processor is
sleeping.
Processor clock
Debug port (AHB-AP) clock
FCLK and HCLK are synchronous to each other. FCLK is a free running version of
HCLK. For more information, see Chapter 7 Power Management. FCLK and HCLK
must be balanced with respect to each other, with equal latencies into Cortex-M3.
The processor is integrated with components for debug and trace. Your macrocell may
contain some, or all, of the clocks shown in Table 6-2.
SWCLK is the serial wire clock. It clocks the SWDIN input to the Serial Wire Debug
Port (SW-DP). It is asynchronous to all other clocks.
TCK is the Trace Access Port (TAP) clock. It clocks the JTAG-DP TAP. It is
asynchronous to all other clocks.
TRACECLKIN is the reference clock for the Trace Port Interface Unit (TPIU). It is
asynchronous to the other clocks.
Note
TCK, SWCLK and TRACECLKIN only have to be driven if your implementation
contains JTAG-DP, SW-DP and TPIU blocks respectively. Otherwise, the clock inputs
must be tied off.
Copyright © 2005, 2006 ARM Limited. All rights reserved.

Table 6-1 Cortex-M3 processor clocks

Table 6-2 Cortex-M3 macrocell clocks

Clock Domain
SWCLK SW-DP
TRACECLKIN TPIU
TCK JTAG-DP
Description
Serial wire clock
Clocks the output of the TPIU
TAP clock
ARM DDI 0337B