Advertisement
2.10
Clocks, and resets
2.10.1
Clocks
2.10.2
Resets
ARM DDI 0275D
This section describes:
•
Clocks
•
Resets.
The ETB11 has three clock domains:
•
TAP controller, clocked by DBGTCK
•
memory-mapped peripheral, clocked by HCLK
•
remainder of the system including ETB11 registers, clocked by CLK.
DBGTCK is synchronous to CLK when used with ETM11RV. Synchronization issues
can therefore be ignored and are not discussed further. See ETM versions and variants
on page 1-5 for details of other ETB products,
HCLK can be synchronous or asynchronous to CLK depending on your system design.
Synchronization logic is provided for asynchronous designs. Register read and write
accesses, and RAM read and write accesses, using the AHB interface are described in:
•
Read transfer on page 2-19
•
Write transfer on page 2-22.
There are the following resets:
•
nRESET resets all of the ETB11 registers in the CLK domain. nRESET must
be synchronized to CLK using the circuit shown in Figure 2-7.
+ve
CLK
•
nDBGTRST is the TAP controller reset signal used to reset the ETB11 TAP
controller and other DBGTCK domain registers. nDBGTRST must be
synchronized to CLK using the circuit shown in Figure 2-7.
Copyright © 2002, 2003 ARM Limited. All rights reserved.
Q
D
Q
Q
Q
DBGnTRST
Functional Description
ETB11
nDBGTRST
D
Q
nRESET
Q
DBGTCK
CLK
Figure 2-7 Example synchronizer
2-17
Advertisement
Chapters
