Rom Memory Table; Table 4-3 Cortex-M3 Rom Table - ARM Cortex-M3 Technical Reference Manual

Memory Map
4.3

ROM memory table

Offset Value
0x000 0xFFF0F003
0x004
0xFFF02003
0x008
0xFFF03003
0x00C
0xFFF01003
0x010 or
0xFFF41002
0x014
or
0xFFF41002
0x018
0
0xFCC
0x1
0xFD0
0x0
0xFD4 0x0
0xFD8 0x0
0xFDC 0x0
0xFE0 0x0
0xFE4 0x0
0xFE8 0x0
0xFEC 0x0
0xFF0
0x0D
4-8
The ROM memory is described in Table 4-3.
Name
NVIC
DWT
FPB
ITM
if present TPIU
003
if present ETM
003
End
MEMTYPE
PID4
PID5
PID6
PID7
PID0
PID1
PID2
PID3
CID0
Copyright © 2005, 2006 ARM Limited. All rights reserved.
Description
Points to the NVIC at
0xE000E000
Points to the Data Watchpoint and Trace block at
Points to the Flash Patch and Breakpoint block at
Points to the Instrumentation Trace block at
Points to the TPIU. Value has bit 0 set to 1 if TPIU is fitted.
TPIU is at .
0xE0040000
Points to the ETM. Value has bit 0 set to 1 if ETM is fitted. ETM
is at 0xE0041000 .
Marks the end of the ROM table. If CoreSight components are
added, they are added starting from this location and the End
marker is moved to the next location after the additional
components.
MEMTYPE field has bit 0 defined for "System memory access"
if 1, debug only if 0.
-
-
-
-
-
-
-
-
-

Table 4-3 Cortex-M3 ROM table

.
0xE0001000
0xE0002000
0xE0000000
ARM DDI 0337B
.
.
.