D9.21 Trcdevaff0, Device Affinity Register 0 - ARM Cortex-A76 Core Technical Reference Manual

D9.21 TRCDEVAFF0, Device Affinity Register 0
The TRCDEVAFF0 provides an additional core identification mechanism for scheduling purposes in a
cluster. TRCDEVAFF0 is a read-only copy of MPIDR accessible from the external debug interface.
Bit field descriptions
The TRCDEVAFF0 is a 32-bit register.
RES1, [31]
U, [30]
RES0, [29:25]
MT, [24]
Aff2, [23:16]
Aff1, [15:8]
Aff0, [7:0]
100798_0300_00_en
31 30 29 25 24 23
U
MT
1
RES
0
RES
Reserved.
RES1
Indicates a single core system, as distinct from core 0 in a cluster. This value is:
Core is part of a multiprocessor system. This is the value for implementations with
0
more than one core, and for implementations with an ACE or CHI master interface.
Core is part of a uniprocessor system. This is the value for single core
1
implementations with an AXI master interface.
Reserved.
RES0
Indicates whether the lowest level of affinity consists of logical cores that are implemented
using a multithreading type approach. This value is:
Performance of cores at the lowest affinity level is largely independent.
0
Affinity level 2. Second highest level affinity field.
Indicates the value read in the CLUSTERIDAFF2 configuration signal.
Affinity level 1. Third highest level affinity field.
Indicates the value read in the CLUSTERIDAFF1 configuration signal.
Affinity level 0. Lowest level affinity field.
Indicates the core number in the Cortex-A76 core. The possible values are:
A cluster with one core only.
0x0
, A cluster with two cores.
0x0 0x1
, , A cluster with three cores.
0x0 0x1 0x2
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D9.21 TRCDEVAFF0, Device Affinity Register 0

16 15
Aff2
Figure D9-20 TRCDEVAFF0 bit assignments
reserved.
Non-Confidential
D9 ETM registers
8 7
Aff1 Aff0
0
D9-524