Rom Memory Table; Table 4-3 Rom Table - ARM Cortex-M3 Technical Reference Manual

4.3

ROM memory table

Offset Value
0x000 0xFFF0F003
or
0x004 0xFFF02002
0x008 0xFFF03002 or
or
0x00C 0xFFF01002
or
0x010 0xFFF41002
0x014 0xFFF42002 or
0
0x018
0xFCC 0x1
0xFD0 0x0
0xFD4 0x0
0xFD8 0x0
0xFDC 0x0
0xFE0 0x0
0xFE4 0x0
0xFE8 0x0
0xFEC 0x0
0xFF0 0x0D
ARM DDI 0337G
Unrestricted Access
Table 4-3 describes the ROM memory.
Name
NVIC
if present DWT
003
003 if present FPB
if present ITM
003
if present TPIU
003
003 if present ETM
End
MEMTYPE
PID4
PID5
PID6
PID7
PID0
PID1
PID2
PID3
CID0
Copyright © 2005-2008 ARM Limited. All rights reserved.
Description
Points to the NVIC at
Points to the Data Watchpoint and Trace block at
Value has bit [0] set if DWT is present.
Points to the Flash Patch and Breakpoint block at
Value has bit [0] set to 1 if FPB is present.
Points to the Instrumentation Trace block at
has bit [0] set if ITM is present.
Points to the TPIU. Value has bit [0] set to 1 if TPIU is present.
TPIU is at
0xE0040000
Points to the ETM. Value has bit [0] set to 1 if ETM is present.
ETM is at
0xE0041000
Marks the end of the ROM table. If CoreSight components are
added, they are added starting from this location and the End
marker is moved to the next location after the additional
components.
Bits [31:1] RAZ. Bit [0] is set when the system memory map is
accessible using the DAP. Bit [0] is clear when only debug
resources are accessible using the DAP.
-
-
-
-
-
-
-
-
-
Non-Confidential

Table 4-3 ROM table

.
0xE000E000
0xE0000000
.
.
Memory Map
.
0xE0001000
0xE0002000 .
. Value
4-7