Figure 3-3 Accessing Translation Table First-Level Descriptors - ARM ARM926EJ-S Technical Reference Manual

Memory Management Unit
3.2.2 First-level fetch
31
Translation base
31
Translation base
31
3.2.3 First-level descriptor
3-8
Bits [31:14] of the TTBR are concatenated with bits [31:20] of the MVA to produce a
30-bit address as shown in Figure 3-3.
31
Translation table base
14 13
14 13
First-level descriptor

Figure 3-3 Accessing translation table first-level descriptors

This address selects a 4-byte translation table entry. This is a first-level descriptor for
either a section or a page table.
The first-level descriptor returned is a section descriptor, a coarse page table descriptor,
or a fine page table descriptor, or is invalid. Figure 3-4 on page 3-9 shows the format of
a first-level descriptor.
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Modified virtual address
20 19
Table index
0
2 1 0
Table index 0 0
0
0
ARM DDI0198D