Table 4-1 Memory Interfaces; Table 4-2 Memory Region Permissions - ARM Cortex-M3 Technical Reference Manual

Memory Map
Code
SRAM
SRAM_bitband
Peripheral
Periph_bitband
External RAM
External Device
Private Peripheral Bus
System
ARM DDI 0337B
Table 4-1 shows the processor interfaces that are addressed by the different memory
map regions
Interface
Instruction fetches are performed over the ICode bus. Data accesses are performed over the
DCode bus.
Instruction fetches and data accesses are performed over the system bus.
Alias region. Data accesses are aliases. Instruction accesses are not aliases.
Instruction fetches and data accesses are performed over the system bus.
Alias region. Data accesses are aliases. Instruction accesses are not aliases.
Instruction fetches and data accesses are performed over the system bus.
Instruction fetches and data accesses are performed over the system bus.
Accesses to ITM, NVIC, FPB, DWT and MPU are performed to the processor internal Private
Peripheral Bus. Accesses to the TPIU, ETM, and System areas of the PPB memory map are
performed over the external Private Peripheral Bus interface.
This memory region is Execute Never (XN), and so instruction fetches are prohibited. This
cannot be changed by an MPU, if present.
System segment for vendor system peripherals. This memory region is Execute Never (XN), and
so instruction fetches are prohibited. This cannot be changed by an MPU, if present.
Table 4-2 shows the permissions of the processor memory regions.
Name
Code
SRAM
SRAM_bitband
Peripheral
Periph_bit band
External RAM
External RAM
Copyright © 2005, 2006 ARM Limited. All rights reserved.

Table 4-2 Memory region permissions

Region
0x00000000-0x1FFFFFFF
0x20000000-0x3FFFFFFF
0x22000000-0x23FFFFFF
0x40000000-0x5FFFFFFF
0x42000000-0x43FFFFFF
0x60000000-0x7FFFFFFF
0x80000000-0x9FFFFFFF
Memory Map

Table 4-1 Memory interfaces

Device type XN Cache
Normal - WT
Normal - WBWA
Internal - -
Device XN -
Internal XN -
Normal - WBWA
Normal - WT
4-3