Table 2-26 Fcse Pid Register Operations; Figure 2-15 Process Id Register Format - ARM ARM926EJ-S Technical Reference Manual

Programmer's Model
31
2-34
FCSE PID Register
Addresses issued by the ARM9EJ-S core in the range 0 to 32MB are translated in
accordance with the value contained in this register. Address A becomes A + (FCSE
PID x 32MB). It is this modified address that is seen by the caches, MMU, and TCM
interface. Addresses above 32MB are not modified. The FCSE PID is a seven-bit field,
enabling 128 x 32MB processes to be mapped.
If the FCSE PID is 0, there is a flat mapping between the virtual addresses output by the
ARM9EJ-S core and the modified virtual addresses used by the caches, MMU, and
TCM interface. The FCSE PID is set to 0 at system reset.
If the MMU is disabled, then no FCSE address translation occurs.
FCSE translation is not applied for addresses used for entry based cache or TLB
maintenance operations. For these operations VA = MVA.
Table 2-26 shows the ARM instructions that can be used to access the FCSE PID
Register.
The format of the FCSE PID Register is shown in Figure 2-15.
25 24
FCSE PID
Performing a fast context switch
You can perform a fast context switch by writing to CP15 register c13 with Opcode_2
= 0. The contents of the caches and the TLB do not have to be flushed after a fast context
switch because they still hold valid address tags. The two instructions after the FCSE
PID has been written have been fetched with the old FCSE PID, as the following code
example shows:
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Table 2-26 FCSE PID Register operations

Function Data
Read FCSE PID FCSE PID
Write FCSE PID FCSE PID
SBZ

Figure 2-15 Process ID Register format

ARM Instruction
MRC p15,0,<Rd>,c13,c0, 0
MCR p15,0,<Rd>,c13,c0, 0
0
ARM DDI0198D