Table 8-14 Interrupt Control State Register Bit Assignments; Figure 8-8 Interrupt Control State Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

Field Name
[31] NMIPENDSET
[30:29] -
[28] PENDSVSET
[27] PENDSVCLR
[26] PENDSTSET
[25] PENDSTCLR
ARM DDI 0337B
Table 8-14 describes the fields of the Interrupt Control State Register.
Type Definition
Read/write Set pending NMI bit:
1 = set pending NMI
0 = do not set pending NMI.
NMIPENDSET pends and activates an NMI. Because NMI is the
highest-priority interrupt, it takes effect as soon as it registers.
- Reserved.
Read/write Set pending pendSV bit:
1 = set pending pendSV
0 = do not set pending pendSV.
Write-only Clear pending pendSV bit:
1 = clear pending pendSV
0 = do not clear pending pendSV.
Read/write Set a pending SysTick bit
1 = set pending SysTick
0 = do not set pending SysTick.
Write-only Clear pending SysTick bit:
1 = clear pending SysTick
0 = do not clear pending SysTick.
Copyright © 2005, 2006 ARM Limited. All rights reserved.

Figure 8-8 Interrupt Control State Register bit assignments

Table 8-14 Interrupt Control State Register bit assignments

Nested Vectored Interrupt Controller
8-19