Dma Signals; Table A-8 Dma Signals; A.9 Dma Signals - ARM ARM966E-S Technical Reference Manual

A.9

DMA Signals

ARM DDI 0186A
DMA signals are listed in Table A-8.
Name Direction
DMAENABLE Input
DMAnREQ Input
DMAA[25:0] Input
DMAnRW Input
DMAMAS[1:0] Input
DMAD[31:0] Input
DMAWait Input
DMAReady Output
DMARData[31:0] Output
Copyright © 2000 ARM Limited. All rights reserved.
Description
Enable ARM966E-S DMA port. Must be tied LOW
if DMA not required.
DMA not memory request. Must be tied HIGH if
DMA not required.
DMA address. Accesses up to 64Mbyte of memory.
Unused address bits must be tied LOW.
DMA write not read:
0 = read
1 = write.
DMA Memory Access Size. Encodes the size of
writes. Reads are always word wide:
00 = byte
01 = halfword
10 = word
11 = reserved.
DMA write data.
DMA Wait. Used to stall the ARM966E-S to allow a
DMA access to take place. This functionality is only
required if the data RAM is single-port. This signal
must be tied LOW if the data RAM is dual-port.
This signal has the same functionality internal to the
ARM966E-S as FIFOFULL.
DMA Ready. Asserted HIGH when the ARM966E-S
is stalled. Only needs to be sampled when the data
RAM is single port, for example when the
ARM966E-S stall was requested by DMAWait.
DMA read data.
Signal Descriptions

Table A-8 DMA signals

A-15