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Core Debug
10.1
About core debug
10.1.1
Halt mode debugging
10.1.2
Exiting core debug
10-2
Core debug is accessed through the core debug registers. Debug access to these registers
is by means of the Advanced High-performance Bus (AHB-AP) port, see AHB-AP on
page 11-39. The processor can access these registers directly over the internal Private
Peripheral Bus (PPB).
Table 10-1 shows the core debug registers.
Address
Type
Read/Write
0xE000EDF0
Write-only
0xE000EDF4
Read/Write
0xE000EDF8
Read/Write
0xE000EDFC
a. Bits 5, 3, 2, 1, 0 are reset by PORESETn. Bit [1] is also reset by SYSRESETn and writing a 1
to the VECTRESET bit of the Application Interrupt and Reset Control Register.
b. Bits 16,17,18,19 are also reset by SYSRESETn and writing a 1 to the VECTRESET bit of the
Application Interrupt and Reset Control Register.
The Debug Fault Status Register is also used for debug purposes. See Debug Fault
Status Register on page 8-38 for more information.
Core debug is an optional component. If core debug is removed then halt mode
debugging is not supported, therefore there is no halt, stepping, or register transfer
functionality. Debug monitor mode is still supported.
The debugger can halt the core by setting the C_DEBUGEN and C_HALT bits of the
Debug Halting Control and Status Register. The core acknowledges when halted by
setting the S_HALT bit of the Debug Halting Control and Status Register.
The core can be single stepped by halting the core, setting the C_STEP bit to 1, and
then clearing the C_HALT bit to 0. The core acknowledges completion of the step and
re-halt by setting the S_HALT bit of the Debug Halting Control and Status Register.
The core can exit Halting debug by clearing the C_DEBUGEN bit in the Debug Halting
and Status Register.
Copyright © 2005-2008 ARM Limited. All rights reserved.
Reset Value
Description
a
Debug Halting Control and Status Register
0x00000000
-
Debug Core Register Selector Register
-
Debug Core Register Data Register
b
Debug Exception and Monitor Control Register.
0x00000000
Non-Confidential
Table 10-1 Core debug registers
ARM DDI 0337G
Unrestricted Access
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