B2.13 Afsr1_El3, Auxiliary Fault Status Register 1, El3 - ARM Cortex-A76 Core Technical Reference Manual

B2.13 AFSR1_EL3, Auxiliary Fault Status Register 1, EL3
AFSR1_EL3 provides additional
taken to EL3. This register is not used in the Cortex-A76 core.
Bit field descriptions
AFSR1_EL3 is a 32-bit register, and is part of:
• The Exception and fault handling registers functional group.
• The Security registers functional group.
• The
IMPLEMENTATION DEFINED
RES0, [31:0]
Configurations
100798_0300_00_en
IMPLEMENTATION DEFINED
functional group.
31
0
RES
Reserved, .
RES0
There are no configuration notes.
Bit fields and details that are not provided in this description are architecturally defined. See the
Arm Architecture Reference Manual Armv8, for Armv8-A architecture profile.
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B2.13 AFSR1_EL3, Auxiliary Fault Status Register 1, EL3

fault status information for exceptions that are
Figure B2-9 AFSR1_EL3 bit assignments
reserved.
Non-Confidential
B2 AArch64 system registers
0
B2-154