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Debug Port
Figure 12-13 on page 12-31 shows the WAIT or FAULT response to a read operation
when overrun detection is enabled, and Figure 12-14 on page 12-31 shows the response
to a write operation when overrun detection is enabled.
Figure 12-13 Serial Wire WAIT or FAULT response to a read operation when overrun detection is enabled
Figure 12-14 Serial Wire WAIT or FAULT response to a write operation when overrun detection is enabled
Protocol Error responses
If SW-DP detects a parity error in the packet request it does not reply to the request.
When the host receives no reply to its request, it must back off, in case the SW-DP
mis-aligned within the packet frame, and could be about to return read data. The
back-off period should correspond to the period required for a read transaction to
complete. After this, it can issue a new transfer request. In this situation it must read the
IDCODE register, see The Identification Code Register, IDCODE on page 12-52. This
is mandated by this specification because a successful read of the IDCODE register
confirms that the target is operational.
If there is no response at the second attempt, the debugger should force a line reset and
then initiate retraining. This is necessary because the SW-DP is in a state where it only
responds to a debug request. If the transfer that resulted in the original protocol error
response was a write you can assume safely that no write occurred. If the original
transfer was a read it is possible that the read was issued to an AP. Although this is
unlikely, the possibility is a significant consideration, because reads are pipelined and
the AP can implement a FIFO.
ARM DDI 0337B
Copyright © 2005, 2006 ARM Limited. All rights reserved.
12-31
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