Figure 5-19 Tcm Test Access Using Bist - ARM ARM926EJ-S Technical Reference Manual

Tightly-Coupled Memory Interface
5-28
This is similar to the previous DMA example. However, for BIST testing it is necessary
for the BIST controller to be able to force the memory chip select to both HIGH and
LOW values. This requirement means that it is necessary to hold the ARM926EJ-S core
in such a state that the internal value of the chip select is guranteed to be LOW. This can
be done by holding the ARM926EJ-S in reset (HRESETn LOW) during TCM memory
BIST testing. Note that this requires that HRESETn cannot also be used as a reset
control to the BIST controller.
Copyright © 2001-2003 ARM Limited. All rights reserved.
HRESETn
ARM926EJ-S
DRDMAADDR[17:0]
DRDMAEN
DRDMACS
DRWBL[3:0]
DRnRW
DRWD[31:0]
DRADDR[17:0]
DRCS
DRWAIT
DRSEQ

Figure 5-19 TCM test access using BIST

BISTRSTn
BIST
BISTADDR[17:0]
BISTEN
BISTCS
BISTWD[31:0]
BISTnRW
BISTWBL[3:0]
BISTRD[31:0]
RD[31:0]
1
WBL[3:0]
0
1
nRW
0
1
WD[31:0]
0
A[17:0]
CS
SRAM
ARM DDI0198D