Table 11-27 Ahb-Ap Register Summary; Ahb Access Port - ARM Cortex-M3 Technical Reference Manual

11.7

AHB Access Port

11.7.1 AHB-AP transaction types
11.7.2 Summary and description of the AHB-AP registers
Name
Control and Status Word (CSW)
Transfer Address (TAR)
Data Read/write (DRW)
Banked Data 0 (BD0)
ARM DDI 0337B
The Advanced High-performance Bus Access Port (AHB-AP) is a debug access port
into Cortex-M3, and provides access to all memory and registers in the system,
including processor registers (through the NVIC). System access is independent of the
processor status. AHB-AP is accessed from either a SW-DP or a JTAG-DP.
AHB-AP is a master into the Bus Matrix. Transactions are made using the AHB-AP
Programmer's Model, see Summary and description of the AHB-AP registers, which
generates AHBLite transactions into the Bus Matrix.
AHB-AP does not do back-to-back transactions on the bus, and so all transactions are
non-sequential. AHB-AP can perform unaligned and bit-band transactions. These are
handled by the Bus Matrix. AHB-AP transactions are not subject to MPU lookups.
AHB-AP transactions bypass the FPB, and so no remapping of AHB-AP transactions
by FPB is possible.
AHB-AP supports a sideband signal, HABORT, which is driven by JTAG/SW-DP
initiated transaction aborts. HABORT is driven into the BusMatrix, which resets the
BusMatrix state, so that the Private Peripheral Bus can be accessed by AHB-AP for "last
ditch" debugging (read/stop/reset the core).
AHB-AP transactions are little endian.
Table 11-27 lists the AHB-AP registers.
Type Address
R/W 0x00
R/W
0x04
R/W
0x0C
R/W 0x10
Copyright © 2005, 2006 ARM Limited. All rights reserved.

Table 11-27 AHB-AP register summary

Reset
Description
value
See Register See AHB-AP Control and Status Word
Register on page 11-36
See AHB-AP Transfer Address Register on
0x00000000
page 11-38
See AHB-AP Data Read/Write Register on
-
page 11-39
- See AHB-AP Banked Data Registers 0-3 on
page 11-39
System Debug
11-35