Table 11-29 Ahb-Ap Control And Status Word Register Bit Assignments; Figure 11-19 Ahb-Ap Control And Status Word Register - ARM Cortex-M3 Technical Reference Manual

31 30
Bits Field
[31:30] -
[29] a
MasterType
[28:26] -
[25] Hprot1
[24] -
[23:12] -
[11:8] Mode
[7] TransINProg
[6] DbgStatus
ARM DDI 0337G
Unrestricted Access
29 28 26 25 24
Hprot1
Reserved
MasterType
Reserved
Table 11-29 describes the bit assignments of the AHB-AP Control and Status Word
Register.

Table 11-29 AHB-AP Control and Status Word Register bit assignments

Function
Reserved. Read as 0b00.
0 = core.
1 = debug.
It cannot be changed if transaction is outstanding. Debugger must first check TransinProg.
Reset value = 0b1.
If the FIXHMASTERTYPE input signal is set to 1 then this register has no affect on the
master value indicated by the transaction. It is always marked as the debugger.
Reserved, 0b000.
User/Privilege control - HPROT[1].
Reset value = 0b1.
Reserved, 0b1.
Reserved, .
0x000
Mode of operation bits:
b0000 = normal download/upload mode
b0001-b1111 are reserved.
Reset value = 0b0000.
Transfer in progress. This field indicates if a transfer is in progress on the APB master port.
Indicates the status of the DAPEN port. If DbgStatus is LOW, no AHB transfers carried out.
1 = AHB transfers permitted.
0 = AHB transfers not permitted.
Copyright © 2005-2008 ARM Limited. All rights reserved.
Reserved

Figure 11-19 AHB-AP Control and Status Word Register

Non-Confidential
12 11 8 7 6 5 4 3 2
MODE
TransInProg
DbgStatus
AddrInc
Reserved
System Debug
0
SIZE
11-41