Figure 11-19 Ahb-Ap Control And Status Word Register - ARM Cortex-M3 Technical Reference Manual

System Debug
Name
Banked Data 1 (BD1)
Banked Data 2 (BD2)
Banked Data 3 (BD3)
Debug ROM Address
Identification Register (IDR)
11-36
Type Address
R/W
0x14
R/W
0x18
R/W 0x1C
RO
0xF8
RO
0xFC
AHB-AP Control and Status Word Register
Use this register to configure and control transfers through the AHB interface.
Figure 11-19 shows the fields of the AHB-AP Control and Status Word Register.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
Table 11-27 AHB-AP register summary
Reset
Description
value
- See AHB-AP Banked Data Registers 0-3 on
page 11-39
- See AHB-AP Banked Data Registers 0-3 on
page 11-39
- See AHB-AP Banked Data Registers 0-3 on
page 11-39
See AHB-AP Debug ROM Address Register
0xE000E000
on page 11-39
See AHB-AP ID Register on page 11-40
0x04770011

Figure 11-19 AHB-AP Control and Status Word Register

ARM DDI 0337B