Figure 5-16 Tcm Subsystem That Uses Wait States For Nonsequential Accesses - ARM ARM926EJ-S Technical Reference Manual

ARM DDI0198D
ARM926EJ-S
IRWAIT
IRSEQ
IRADDR[17:0]
IRRD[31:0]

Figure 5-16 TCM subsystem that uses wait states for nonsequential accesses

The address and chip-select inputs to the ROM are pipelined with respect to the
ARM926EJ-S TCM interface outputs. An address incrementer is used to generate
sequential addresses. The output of the incrementer is captured at the end of every cycle
where the ROM CS chip select is active. The address source for the ROM is switched
over to the registered version of IRADDR when a nonsequential access occurs.
Figure 5-17 on page 5-26 shows the timing of the ROM address, chip-select, and read
data relative to the ARM926EJ-S TCM interface signals. The address supplied to the
ROM can either be behind, in sync with, or ahead of IRADDR, depending on the type
of memory access and the presence of idle cycles.
Copyright © 2001-2003 ARM Limited. All rights reserved.
IRCS
Tightly-Coupled Memory Interface
CS
1
A
0
EN
+1
RD
ROM
5-25