12.12 Memory Attributes; Table 12-3 Memory Attributes - ARM Cortex-M3 Technical Reference Manual

12.12 Memory attributes

ARM DDI 0337G
Unrestricted Access
The processor exports memory attributes on the System bus by the addition of a
sideband bus, MEMATTR.
Table 12-3 shows the relationship between MEMATTR[0] and HPROT[3:2].
MEMATTR[0]
0
0
0
1
1
1
0
1
Copyright © 2005-2008 ARM Limited. All rights reserved.
HPROT[3] HPROT[2]
0 0
0 1
1 0
0 0
0 1
1 0
1 1
1 1
Non-Confidential

Table 12-3 Memory attributes

Description
Strongly ordered
Device
L1 cacheable, L2 not cacheable
Invalid
Invalid
Cache WT, allocate on read
Cache WB, allocate on read and write
Cache WB, allocate on read
Bus Interface
12-15