Table 2-22 Tcm Region Register Instructions - ARM ARM926EJ-S Technical Reference Manual

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ARM DDI0198D

For each of the cache lines to be locked down in cache way i:

•

If a DCache is being locked down, use an LDR instruction to load a word

from the memory cache line to ensure that the memory cache line is loaded

into the cache.

•

If an ICache is being locked down, use the register c7 MCR prefetch ICache

line (CRm == c13, Opcode2 == 1) to fetch the memory cache line into the

cache.

Write to register c9, CRm == 0 setting L == 1 for bit i and restoring all the other

bits to the values they had before the lockdown routine was started.

Cache unlock procedure

To unlock the locked down portion of the cache, write to register c9 setting L == 0 for

the appropriate bit. For example, the following sequence sets the L bit to 0 for way 0 of

the ICache, unlocking way 0:

MRC p15, 0, <Rn>, c9, c0, 1;

BIC <Rn>, <Rn>, 0x01 ;

MCR p15, 0, <Rn>, c9, c0, 1;

TCM Region Register c9

The ARM926EJ-S processor supports physically-indexed, physically-tagged TCM.

The TCM Region Register supports one region of instruction TCM and one region of

data TCM. The minimum size of TCM region that can be supported is 4KB. The TCM

Status Register indicates if TCM memories are attached (see TCM Status Register c0 on

page 2-12). The size of each TCM region is defined by the DRSIZE and IRSIZE input

pins.

The data TCM is always disabled at reset. The instruction TCM is enabled at reset if the

INITRAM pin is HIGH. This enables booting from the instruction TCM and sets the

ITCM enable bit in the ITCM region register. You can use the TCM Region Register

instructions listed in Table 2-22.

Function

Read data TCM Region Register

Write data TCM Region Register

Read instruction TCM Region Register

Write instruction TCM Region Register