Table 8-19 Configuration Control Register Bit Assignments; Figure 8-13 Configuration Control Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

31
Bits Field
[31:10] _
[9] STKALIGN
[8] BFHFNMIGN
[7:5] -
[4] DIV_0_TRP
ARM DDI 0337G
Unrestricted Access
Figure 8-13 shows the bit assignments of the Configuration Control Register.
Table 8-19 describes the bit assignments of the Configuration Control Register.
Function
Reserved.
1 = on exception entry, the SP used prior to the exception is adjusted to be 8-byte
aligned and the context to restore it is saved. The SP is restored on the associated
exception return.
0 = only 4-byte alignment is guaranteed for the SP used prior to the exception on
exception entry.
When enabled, this causes handlers running at priority -1 and -2 (Hard Fault, NMI,
and FAULTMASK escalated handlers) to ignore Data Bus faults caused by load
and store instructions. When disabled, these bus faults cause a lock-up. You must
only use this enable with extreme caution. All data bus faults are ignored – you
must only use it when the handler and its data are in absolutely safe memory. Its
normal use is to probe system devices and bridges to detect control path problems
and fix them.
Reserved.
Trap on Divide by 0. This enables faulting/halting when an attempt is made to
divide by 0. The relevant Usage Fault Status Register bit is DIVBYZERO, see
Usage Fault Status Register on page 8-35.
Copyright © 2005-2008 ARM Limited. All rights reserved.
Reserved
BFHFNMIGN
DIV_0_TRP
UNALIGN_TRP
USERSETMPEND
NONBASETHRDENA

Figure 8-13 Configuration Control Register bit assignments

Table 8-19 Configuration Control Register bit assignments

Non-Confidential
Nested Vectored Interrupt Controller
10 9 8 7
Res
STKALIGN
Reserved
5 4 3 2 1 0
8-27