Table 8-18 Configuration Control Register Bit Assignments; Figure 8-12 Configuration Control Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

Field Name
[8] BFHFNMIGN
[4] DIV_0_TRP
ARM DDI 0337B
The register address, access type, and Reset state are:
Address
0xE000ED14
Access Read/write
Reset state
0x00000000
Figure 8-12 shows the fields of the Configuration Control Register.

Figure 8-12 Configuration Control Register bit assignments

Table 8-18 describes the fields of the Configuration Control Register.
Definition
When enabled, this causes handlers running at priority -1 and -2 (Hard Fault, NMI,
and FAULTMASK escalated handlers) to ignore Data Bus faults caused by load and
store instructions. When disabled, these bus faults cause a lock-up. This enable must
be used with extreme caution. All data bus faults are ignored – it must only be used
when the handler and its data are in absolutely safe memory. Its normal use is to
probe system devices and bridges to detect control path problems and fix them.
Trap on Divide by 0. This enables faulting/halting when an attempt is made to divide
by 0. The relevant Usage Fault Status Register bit is DIVBYZERO, see Usage Fault
Status Register on page 8-33.
Copyright © 2005, 2006 ARM Limited. All rights reserved.

Table 8-18 Configuration Control Register bit assignments

Nested Vectored Interrupt Controller
8-25