ST STM32L4+ Series Reference Manual page 599

RM0432
Bits 5:4 ISIZE[1:0]: Instruction size
This bit defines instruction size:
00: 8-bit instruction
01: 16-bit instruction
10: 24-bit instruction
11: 32-bit instruction
This field can be written only when BUSY = 0.
Bit 3 IDTR: Instruction double transfer rate
This bit sets the DTR mode for the instruction phase.
0: DTR mode disabled for instruction phase
1: DTR mode enabled for instruction phase
This field can be written only when BUSY = 0.
Bits 2:0 IMODE[2:0]: Instruction mode
This field defines the Instruction phase's mode of operation.
000: No instruction
001: Instruction on a single line
010: Instruction on two lines
011: Instruction on four lines
100: Instruction on eight lines
101-111: Reserved
This field can be written only when BUSY = 0.
19.6.20 OCTOSPI write timing configuration register (OCTOSPI_WTCR)
Address offset: 0x0188
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:5 Reserved, must be kept at reset value.
Bits 4:0 DCYC[4:0]: Number of dummy cycles
This field defines the duration of the dummy phase.
In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended
to have at least 5 dummy cycles when using memories with DQS activated.
This field can be written only when BUSY = 0.
27 26 25 24
Res. Res. Res. Res.
11 10 9 8
Res. Res. Res. Res.
RM0432 Rev 6
Octo-SPI interface (OCTOSPI)
23 22 21 20
Res. Res. Res. Res.
7 6 5 4
Res. Res. Res.
rw
19 18 17 16
Res. Res. Res. Res.
3 2 1 0
DCYC[4:0]
rw rw rw rw
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