ST STM32L4+ Series Reference Manual page 928

DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only
a High-Speed transmission. It also performs data splitting between available D-PHY
lanes for High-Speed transmission.
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The Packet Handler schedules the activities inside the link. It performs several
functions based on the interfaces that are currently operational and the video
transmission mode that is used (burst mode or non-burst mode with sync pulses or
sync events). It builds long or short packet generating correspondent ECC and CRC
codes. This block also performs the following functions:
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The APB-to-Generic block bridges the APB operations into FIFOs holding the Generic
commands. The block interfaces with the following FIFOS:
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The Error Management notifies and monitors the error conditions on the DSI link. It
controls the timers used to determine if a timeout condition occurred, performing an
internal soft reset and triggering an interruption notification.
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packet reception
validation of packet header by checking the ECC
header correction and notification for single-bit errors
termination of reception
multiple header error notification
depending on the virtual channel of the incoming packet, the handler routes the
output data to the respective port.
Command FIFO
Write payload FIFO
Read payload FIFO
RM0432 Rev 6
RM0432