ST STM32L4+ Series Reference Manual page 511

RM0432
Bit number
31:24
23:22
21
20
19
18:16
15
14
13
12
11
10
9
8
7
6
5:4
3:2
1
0
Bit number
31:30
29:28
27:24
23:20
19:16
15:8
7:4
3:0
Table 95. FMC_BCRx bitfields (mode A)
Bit name
Reserved 0x000
NBLSET[1:0] As needed
WFDIS As needed
CCLKEN As needed
CBURSTRW 0x0 (no effect in Asynchronous mode)
CPSIZE 0x0 (no effect in Asynchronous mode)
ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.
EXTMOD 0x1
WAITEN 0x0 (no effect in Asynchronous mode)
WREN As needed
WAITCFG Don't care
Reserved 0x0
WAITPOL Meaningful only if bit 15 is 1
BURSTEN 0x0
Reserved 0x1
FACCEN Don't care
MWID As needed
MTYP As needed, exclude 0x2 (NOR Flash memory)
MUXEN 0x0
MBKEN 0x1
Table 96. FMC_BTRx bitfields (mode A)
Bit name
Duration of the data hold phase (DATAHLD HCLK cycles for read
DATAHLD
accesses).
ACCMOD 0x0
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
Duration of the second access phase (DATAST HCLK cycles) for read
DATAST
accesses.
ADDHLD Don't care
Duration of the first access phase (ADDSET HCLK cycles) for read
accesses.
ADDSET
Minimum value for ADDSET is 0.
RM0432 Rev 6
Flexible static memory controller (FSMC)
Value to set
Value to set
511/2301
554