ST STM32L4+ Series Reference Manual page 292

Reset and clock control (RCC)
Bit 11 WWDGEN: Window watchdog clock enable
Bit 10 RTCAPBEN: RTC APB clock enable
Bits 9:6 Reserved, must be kept at reset value.
Bit 5 TIM7EN: TIM7 timer clock enable
Bit 4 TIM6EN: TIM6 timer clock enable
Bit 3 TIM5EN: TIM5 timer clock enable
Bit 2 TIM4EN: TIM4 timer clock enable
Bit 1 TIM3EN: TIM3 timer clock enable
Bit 0 TIM2EN: TIM2 timer clock enable
6.4.20 APB1 peripheral clock enable register 2 (RCC_APB1ENR2)
Address offset: 0x5C
Reset value: 0x00000 0000
Access: no wait state, word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral registers read or write access is not
supported.
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Set by software to enable the window watchdog clock. Reset by hardware system reset.
This bit can also be set by hardware if the WWDG_SW option bit is reset.
0: Window watchdog clock disabled
1: Window watchdog clock enabled
Set and cleared by software
0: RTC APB clock disabled
1: RTC APB clock enabled
Set and cleared by software.
0: TIM7 clock disabled
1: TIM7 clock enabled
Set and cleared by software.
0: TIM6 clock disabled
1: TIM6 clock enabled
Set and cleared by software.
0: TIM5 clock disabled
1: TIM5 clock enabled
Set and cleared by software.
0: TIM4 clock disabled
1: TIM4 clock enabled
Set and cleared by software.
0: TIM3 clock disabled
1: TIM3 clock enabled
Set and cleared by software.
0: TIM2 clock disabled
1: TIM2 clock enabled
RM0432 Rev 6
RM0432